Gate control for staggered stacked field-effect transistors
AssigneeInternational Business Machines Corporation
InventorsGenevieve Antoinette Kane, Manasa Medikonda, Md Nabil Azad, Shravana Kumar Katakam, Nicholas Latham, Indira Seshadri, Tao Li
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Abstract
A semiconductor device includes a first transistor comprising a first gate region, and a second transistor comprising a second gate region. The second transistor is stacked on the first transistor in a staggered configuration. A dielectric bonding layer is between the first transistor and the second transistor, and a gate cut portion is along a side of the first gate region and a side of the second gate region. A gate contact is connected to at least one of the first gate region and the second gate region.
Claims20
A semiconductor device, comprising:
- a first transistor comprising a first gate region;
- a second transistor comprising a second gate region, wherein the second transistor is stacked on the first transistor in a staggered configuration;
- a dielectric bonding layer between the first transistor and the second transistor;
- a gate cut portion along a side of the first gate region and a side of the second gate region;
- and
- a gate contact connected to at least one of the first gate region and the second gate region.
A semiconductor device, comprising:
- a first pair of transistors, wherein the first pair of transistors comprises a second transistor stacked on a first transistor in a staggered configuration, and wherein the first transistor comprises a first gate region and the second transistor comprises a second gate region;
- a second pair of transistors, wherein the second pair of transistors comprises a fourth transistor stacked on a third transistor in a staggered configuration, and wherein the third transistor comprises a third gate region and the fourth transistor comprises a fourth gate region;
- a first gate contact electrically connected to the first gate region and the second gate region;
- a second gate contact electrically connected to the third gate region;
- and
- a third gate contact electrically connected to the fourth gate region.
A semiconductor device, comprising:
- a first transistor comprising a first gate region;
- a second transistor comprising a second gate region, wherein the second transistor is stacked on the first transistor in a staggered configuration;
- a dielectric bonding layer between the first transistor and the second transistor;
- a dielectric trench along a side of the first gate region and a side of the second gate region;
- and
- at least one gate contact contacting one of the first gate region and the second gate region.
Dependencies are inferred from the claim text.