US 2024/0194692 A1Published application

Display panel

AssigneeAUO Corporation

InventorsHsiu-Chun Hsieh, Shu-Hui Huang, Yi-Wei Chen

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Abstract

A display panel includes a substrate, first, second, and third data lines, scan lines, a first active device, a second active device, and pixel electrodes. The first and the third data lines have a first polarity. The second data line has a second polarity. The first polarity is different from the second polarity. A source electrode of the first active device disposed between the first data line and the second data line is electrically connected to the first data line. An extension region of the semiconductor pattern of the first active device extends toward and overlaps the second data line. A source electrode of the second active device disposed between the second data line and the third data line is electrically connected to the second data line. An extension region of the semiconductor pattern of the second active device extends toward and overlaps the third data line.

Claims20

Dependent claims

A display panel, comprising:

a substrate;
a plurality of data lines, arranged at intervals on the substrate and comprising a first data line, a second data line, and a third data line disposed in sequence, wherein each of the first data line and the third data line has a first polarity, the second data line has a second polarity, and the first polarity is different from the second polarity;
a plurality of scan lines, arranged at intervals on the substrate, wherein the data lines and the scan lines are intersected to define a plurality of pixel regions;
a plurality of active devices, respectively disposed in the pixel regions, each of the active devices comprising a semiconductor pattern, a source electrode, a drain electrode, and a gate electrode, wherein the gate electrode is electrically connected to one of the scan lines, the semiconductor pattern has a source region and a drain region respectively connected to the source electrode and the drain electrode, a channel region connected between the source region and the drain region, and an extension region extending from the drain region, the active devices comprising:
a first active device, disposed between the first data line and the second data line, wherein the source electrode of the first active device is electrically connected to the first data line, and the extension region of the semiconductor pattern of the first active device extends toward the second data line and overlaps the second data line;
and
a second active device, disposed between the second data line and the third data line, wherein the source electrode of the second active device is electrically connected to the second data line, and the extension region of the semiconductor pattern of the second active device extends toward the third data line and overlaps the third data line;
and
a plurality of pixel electrodes, respectively disposed in the pixel regions and electrically connected to the drain electrodes of the active devices, respectively.

6 more elements

A display panel, comprising:

a substrate;
a plurality of first data lines and a plurality of second data lines, alternately arranged on the substrate, wherein each of the first data lines has a first polarity, each of the second data lines has a second polarity, and the first polarity is different from the second polarity;
a plurality of scan lines, arranged at intervals on the substrate, wherein the scan lines intersect with the first data lines and the second data lines;
a first pixel structure, disposed between one of the first data lines and one of the second data lines and having a first active device and a first pixel electrode, wherein the first active device comprises a first semiconductor pattern, a first source electrode, a first drain electrode, and a first gate electrode, the first source electrode is electrically connected to the one of the first data lines and a first source region of the first semiconductor pattern, the first drain electrode is electrically connected to the first pixel electrode and a first drain region of the first semiconductor pattern, the first gate electrode overlaps a first channel region of the first semiconductor pattern, and the first channel region is connected between the first source region and the first drain region;
and
a second pixel structure, disposed between the one of the second data lines and another of the first data lines and having a second active device and a second pixel electrode, wherein the second active device comprises a second semiconductor pattern, a second source electrode, a second drain electrode, and a second gate electrode, the second source electrode is electrically connected to the one of the second data lines and a second source region of the second semiconductor pattern, the second drain electrode is electrically connected to the second pixel electrode and a second drain region of the second semiconductor pattern, the second gate electrode overlaps a second channel region of the second semiconductor pattern, and the second channel region is connected between the second source region and the second drain region,
wherein the first semiconductor pattern has a first extension region extending from the first drain region, the second semiconductor pattern has a second extension region extending from the second drain region, the first extension region of the first semiconductor pattern extends towards the one of the second data lines and overlaps the one of the second data lines, and the second extension region of the second semiconductor pattern extends towards the another of the first data lines and overlaps the another of the first data lines.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/089,538Filed 27 Dec 2022
Priority: TW 11114771513 Dec 2022
Published: 13 Jun 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10D 86/60
Characterised by multiple TFTs: wherein the TFTs are in active matrices
G02F 1/134309
Electrodes: characterised by their geometrical arrangement
G02F 1/136209
Active matrix addressed cells: light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally…
G02F 1/136286
Active matrix addressed cells: wiring, e.g. gate line, drain line