Local interconnect structure

An apparatus, comprising:

• a first fin field effect transistor (finFET) with a first gate terminal, a first source/drain terminal connected to a first reference metal line through a first via, and a second source/drain terminal;
• a second finFET with a second gate terminal, a third source/drain terminal connected to a second reference metal line through a second via, and a fourth source/drain terminal;
• a local interconnect structure routed at a same interconnect level as the first and second reference lines and connected to the first and second gate terminals through one or more third vias;
• a first interconnect structure routed above the local interconnect structure and connected to the third source/drain terminal through the second via;
• and
• a second interconnect structure routed above the local interconnect structure and at a same interconnect level as the first interconnect structure.

A device, comprising:

• a first transistor with a first gate terminal, a first source/drain terminal connected to a first reference metal line, and a second source/drain terminal;
• a second transistor with a second gate terminal, a third source/drain terminal connected to a second reference metal line, and a fourth source/drain terminal;
• a local interconnect structure connected to the first and second gate terminals;
• a first interconnect structure connected to the third source/drain terminal and the second reference metal line;
• and
• a second interconnect structure routed above the local interconnect structure and at a same interconnect level as the first interconnect structure, wherein:
• the local interconnect structure, the first reference metal line, and the second reference metal line are routed at a first level, and
• the first interconnect structure and the second interconnect structure are routed at a second level.