Preventing source/drain epi merge without cell size increase

A method of preventing a source/drain (S/D) epi merge, comprising:

• providing a first nanosheet fin including a first field effect transistor (FET) having a first gate stack, on a substrate;
• and
• providing a second nanosheet fin including a second FET having a second gate stack on the substrate adjacent to the first nanosheet fin,
• wherein a first top of the first gate stack is a different height than a second top of the second gate stack.

A method of forming a semiconductor device, the method comprising:

• forming a stepped portion on a substrate surface;
• forming a first gate nanosheet stack with alternating layers of different semiconductor materials on the stepped portion of the substrate surface;
• forming a second nanosheet gate stack with alternating layers of different semiconductor materials on a non-stepped portion of the substrate surface;
• patterning the first nanosheet gate stack and the second nanosheet gate stack to create respective nanosheet fins, wherein an upper surface of a first nanosheet fin is higher than an upper surface of a second nanosheet fin;
• and
• growing an epitaxial source/drain (S/D) on each of the first nanosheet fin and the second nanosheet fin.