Integration of finfet and gate-all-around devices

An electronic device, comprising:

• a chip package comprising one or more dies, at least one of the one or more dies comprising
• a substrate;
• a first semiconductor device on the substrate and having a semiconductor fin extending in a first direction between a first source region and a first drain region, and a first gate structure extending in a second direction over the semiconductor fin, the first gate structure having a first gate dielectric structure and a first gate electrode on the first gate dielectric structure;
• and
• a second semiconductor device on the substrate and having a plurality of semiconductor nanoribbons extending in the first direction between a second source region and a second drain region, and a second gate structure extending in the second direction over the plurality of semiconductor nanoribbons, the second gate structure having a second gate dielectric structure and a second gate electrode on the second gate dielectric structure;
• wherein the first gate dielectric structure includes a first gate oxide layer and the second gate dielectric structure includes a second gate oxide layer, wherein the first gate oxide layer is at least 2 nm thicker than the second gate oxide layer.

An integrated circuit comprising:

• a substrate including a first subfin region and a second subfin region;
• a first semiconductor device having a semiconductor fin above the first subfin region and extending in a first direction between a first source region and a first drain region, and a first gate structure extending in a second direction over the semiconductor fin, the first gate structure having a first gate dielectric structure and a first gate electrode on the first gate dielectric structure;
• a second semiconductor device having a plurality of semiconductor nanoribbons above the second subfin region and extending in the first direction between a second source region and a second drain region, and a second gate structure extending in the second direction over the plurality of semiconductor nanoribbons, the second gate structure having a second gate dielectric structure and a second gate electrode on the second gate dielectric structure;
• a first dielectric layer adjacent to the first subfin region, and
• a second dielectric layer adjacent to at least a portion of the second subfin region, the second dielectric layer having a greater thickness than the first dielectric layer.