Transistor configurations for multi-deck memory devices

An apparatus, comprising:

• a first silicon substrate;
• a first plurality of transistors formed at least in part by doped portions of the first silicon substrate;
• a first deck of memory cells above and coupled with the first plurality of transistors;
• a second deck of memory cells above the first deck of memory cells;
• a second silicon substrate above the second deck of memory cells;
• and
• a second plurality of transistors formed at least in part by doped portions of the second silicon substrate and coupled with the second deck of memory cells.

A memory system formed by a process comprising:

• forming a first silicon substrate;
• forming a first plurality of transistors formed at least in part by doped portions of the first silicon substrate;
• forming a first deck of memory cells above and coupled with the first plurality of transistors;
• forming a second deck of memory cells above the first deck of memory cells;
• bonding a second silicon substrate above the second deck of memory cells;
• and
• forming a second plurality of transistors formed at least in part by doped portions of the second silicon substrate and coupled with the second deck of memory cells.