Semiconductor package including a plurality of different stacked chips and method of manufacturing the semiconductor package

A semiconductor package comprising:

• first, second, third and fourth semiconductor chips sequentially stacked on one another via conductive connection members,
• wherein each of the first, second, third and fourth semiconductor chips includes a substrate having a first surface and a second surface opposite to each other, and signal chip pads and dummy chip pads provided on the first surface of the substrate,
• wherein each of the conductive connection members include first conductive bumps and second conductive bumps, wherein the first conductive bumps are disposed on the signal chip pads, and wherein second conductive bumps are disposed on the dummy chip pads,
• wherein each of the first conductive bumps includes a signal bump pad and a first solder bump, wherein the signal bump pad is provided on the signal chip pad and has a dimple in an upper portion thereof, and wherein the first solder bump is provided on the signal bump pad, and
• wherein each of the second conductive bumps includes a thermal bump pad and a second solder bump, wherein the thermal bump pad is provided on the dummy chip pad and has a flat upper surface, and wherein the second solder bump is provided on the thermal bump pad.

A semiconductor package comprising:

• a buffer die;
• first, second, third and fourth memory dies sequentially stacked on the buffer die via conductive connection members;
• and
• adhesive layers disposed between the first to fourth memory dies and attaching the first, second, third and fourth memory dies to each other,
• wherein each of the first, second, third and fourth memory dies includes a substrate having a first surface and a second surface opposite to the first surface and signal chip pads and dummy chip pads provided on the substrate,
• wherein the conductive connection members include first conductive bumps and second conductive bumps, wherein the first conductive bumps are disposed on the signal chip pads, and the second conductive bumps are disposed on the dummy chip pads,
• wherein each of the first conductive bumps includes a signal bump pad and a first solder bump, wherein the signal bump pad is provided on the signal chip pad and has a dimple in an upper portion thereof, and the first solder bump is provided on the signal bump pad, and
• wherein each of the second conductive bumps includes a thermal bump pad and a second solder bump, wherein the thermal bump pad is provided on the dummy chip pad and has a flat upper surface, and the second solder bump is provided on the thermal bump pad.