Substrate for semiconductor package and semiconductor package including the same

A semiconductor package comprising:

• a substrate including a plurality of bonding terminals and a plating line on one surface of the substrate;
• a first semiconductor chip that is mounted on the one surface of the substrate and includes a plurality of bonding pads formed near at least one edge on a top surface of the first semiconductor chip;
• and
• a second semiconductor chip that is mounted on the one surface of the substrate at a distance from the first semiconductor chip, and includes a plurality of bonding pads formed near at least one edge on a top surface of the second semiconductor chip,
• wherein,
• the plurality of bonding terminals are between the first semiconductor chip and the second semiconductor chip and are connected to the plurality of bonding pads of the first semiconductor chip and the plurality of bonding pads of the second semiconductor chip by wires,
• the plating line is between the plurality of bonding terminals and the first semiconductor chip and is connected to each of the plurality of bonding terminals, and
• a plating line removal region is between the first semiconductor chip and the plurality of bonding terminals and is free of a portion of the plating line so that each of the plurality of bonding terminals is electrically isolated.

A semiconductor package comprising:

• a substrate that includes connection terminals on a bottom surface that are configured for connection with an external device, bonding terminals on a top surface, which are connected to a semiconductor chip by wires, and via holes and conductive lines configured to facilitate electrical connections to the connection terminals and the bonding terminals;
• and
• a first semiconductor chip and a second semiconductor chip that are arranged along a length direction of the substrate and have substantially a same width as a width of the substrate,
• wherein,
• a plurality of bonding pads are arranged along a width direction of the first semiconductor chip near one edge of a top surface thereof facing the second semiconductor chip,
• a plurality of bonding pads are arranged along a width direction of the second semiconductor chip near one edge of a top surface thereof facing the first semiconductor chip,
• a plurality of bonding terminals are arranged along a width direction of the substrate between the first semiconductor chip and the second semiconductor chip,
• the plurality of bonding terminals are connected to the plurality of bonding pads of the first semiconductor chip and the plurality of bonding pads of the second semiconductor chip by wires,
• all of the plurality of bonding terminals are connected to at least one plating line, which is configured to supply electricity for electroplating, and is on the substrate between the plurality of bonding terminals and the first semiconductor chip,
• a plating line removal region, which is free of a portion of the at least one plating line, is between the first semiconductor chip and the plurality of bonding terminals to electrically separate the plurality of bonding terminals from each other,
• a distance between the second semiconductor chip and the plurality of bonding terminals is less than one-third of a distance between the first semiconductor chip and the plurality of bonding terminals, and
• the distance between the first semiconductor chip and the plurality of bonding terminals is 150 μm or more and the distance between the second semiconductor chip and the plurality of bonding terminals is 150 μm or less.