Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorsSang Cheon PARK, Chungsun Lee, Soohwan Lee, Young Kun Jee
Life of this patent
Estimating the term…
Abstract
Provided is a semiconductor chip stack structure including a plurality of first semiconductor chip dies stacked in a vertical direction, and one or more second semiconductor chip dies between adjacent first semiconductor chip dies among the plurality of first semiconductor chip dies, wherein a thickness of each second semiconductor chip die of the one or more second semiconductor chip dies is greater than a thickness of each first semiconductor chip die of the plurality of first semiconductor chip dies in the vertical direction.
Claims20
A semiconductor chip stack structure comprising:
- a plurality of first semiconductor chip dies stacked in a vertical direction;
- and
- one or more second semiconductor chip dies between adjacent first semiconductor chip dies among the plurality of first semiconductor chip dies,
- wherein a thickness of each second semiconductor chip die of the one or more second semiconductor chip dies is greater than a thickness of each first semiconductor chip die of the plurality of first semiconductor chip dies in the vertical direction.
A semiconductor package comprising:
- an interposer;
- a plurality of semiconductor chip stack structures on the interposer, each semiconductor chip stack structure of the plurality of semiconductor chip stack structures comprising a plurality of first semiconductor chip dies stacked in a vertical direction, and one or more second semiconductor chip dies between adjacent first semiconductor chip dies among the plurality of first semiconductor chip dies;
- a third semiconductor chip on the interposer;
- and
- an encapsulant on the interposer, the plurality of semiconductor chip stack structures, and the third semiconductor chip,
- wherein a thickness of each second semiconductor chip die of the one or more second semiconductor chip dies is greater than a thickness of each first semiconductor chip die of the plurality of first semiconductor chip dies in the vertical direction.
A semiconductor package comprising:
- a substrate;
- an interposer on the substrate;
- a plurality of connection members electrically connecting the substrate and the interposer;
- a plurality of semiconductor chip stack structures directly on the interposer, each of the semiconductor chip stack structures of the plurality of semiconductor chip stack structures comprising a plurality of first semiconductor chip dies stacked in a vertical direction, and one or more second semiconductor chip dies between adjacent first semiconductor chip dies among the plurality of first semiconductor chip dies;
- a third semiconductor chip on the interposer;
- and
- an encapsulant on the interposer, the plurality of semiconductor chip stack structures, and the third semiconductor chip,
- wherein a thickness of each second semiconductor chip die of the one or more second semiconductor chip dies is greater than a thickness of each first semiconductor chip die of the plurality of first semiconductor chip dies in the vertical direction.
Dependencies are inferred from the claim text.