Semiconductor chip and semiconductor package including the same

A semiconductor chip comprising:

• a semiconductor substrate including an active surface and an inactive surface facing the active surface;
• a multi wiring layer arranged on the active surface of the semiconductor substrate, and including at least two layers of each of a conductive wiring and a dummy wiring;
• a lower protection layer including, therein, a conductive medium pad connected to the conductive wiring, and a dummy medium pad connected to the dummy wiring, the lower protection layer being arranged on a front surface of the multi wiring layer;
• an upper protection layer on the inactive surface of the semiconductor substrate;
• a plurality of through vias including a plurality of power through vias, a plurality of signal through vias, and a plurality of dummy through vias, and configured to penetrate the semiconductor substrate and the upper protection layer;
• and
• a plurality of back side pads including a plurality of back side power pads respectively connected to the plurality of power through vias, a plurality of back side signal pads respectively connected to the plurality of signal through vias, and a plurality of back side dummy pads respectively connected to the plurality of dummy through vias, the plurality of back side pads being arranged on a rear surface of the upper protection layer,
• wherein at least one of the plurality of back side power pads is connected to at least one of the plurality of back side dummy pads.

A semiconductor package comprising:

• a first semiconductor chip;
• and
• a second semiconductor chip on the first semiconductor chip,
• wherein the first semiconductor chip comprises:
• a first semiconductor substrate including a first active surface and a first inactive surface, which are opposite to each other;
• a first dummy wiring arranged in a first multi wiring layer on the first active surface of the first semiconductor substrate;
• a plurality of first back side dummy pads arranged on the first inactive surface of the first semiconductor substrate;
• and
• a plurality of first dummy through vias configured to penetrate the first semiconductor substrate and connected to the first dummy wiring and the plurality of first back side dummy pads,
• wherein the second semiconductor chip comprises:
• a second semiconductor substrate including a second active surface and a second inactive surface, which are opposite to each other;
• a second dummy wiring arranged in a second multi wiring layer on the second active surface of the second semiconductor substrate;
• and
• a plurality of second front side dummy pads connected to the second dummy wiring, and arranged on a front surface of the second multi wiring layer, and
• wherein the plurality of first back side dummy pads are respectively connected to the plurality of second front side dummy pads.