Semiconductor device

A semiconductor device comprising:

• a semiconductor substrate having a first surface and a second surface facing the first surface and including, in a plan view, a main chip region and a sealing region surrounding the main chip region;
• a front wiring layer on the first surface of the semiconductor substrate and including a front wiring structure in the main chip region;
• a back wiring layer on the second surface of the semiconductor substrate and including a power wiring structure in the main chip region;
• a front ring structure in the front wiring layer of the sealing region;
• and
• a back ring structure in the back wiring layer of the sealing region,
• the front ring structure including, in a plan view, a front inner ring structure surrounding the main chip region and a front outer ring structure surrounding the front inner ring structure, and
• the back ring structure including, in a plan view, a back inner ring structure surrounding the main chip region and a back outer ring structure surrounding the back inner ring structure.

A semiconductor device comprising:

• a semiconductor substrate having a first surface and a second surface facing the first surface and including, in a plan view, a main chip region and a sealing region surrounding the main chip region;
• a front wiring layer on the first surface of the semiconductor substrate and including a front wiring structure in the main chip region and a front insulating layer covering the front wiring structure;
• a back wiring layer on the second surface of the semiconductor substrate and including a power wiring structure in the main chip region and a back insulating layer covering the power wiring structure;
• a power through via passing through the semiconductor substrate in a vertical direction, the power through via being configured to connect the front wiring structure to the power wiring structure;
• a front ring structure in the front wiring layer of the sealing region and including, in a plan view, a front inner ring structure surrounding the main chip region and a front outer ring structure surrounding the front inner ring structure;
• and
• a back ring structure in the back wiring layer of the sealing region and including, in a plan view, a back inner ring structure surrounding the main chip region and a back outer ring structure surrounding the back inner ring structure.