Semiconductor structure, three-dimensional memory, memory system, and electronic device

A three-dimensional (3D) memory, comprising:

• a semiconductor structure comprising:
• a stack structure comprising gate layers and first dielectric layers disposed alternately;
• first gate isolation structures extending along a first direction and arranged at intervals along a second direction, the first gate isolation structures dividing the stack structure into at least one block comprising a memory region and a connection region that are distributed along the first direction, the first direction being perpendicular to the second direction;
• and
• conductive structures in the connection region, each conductive structure being electrically connected with one gate layer, and the different conductive structures being electrically connected with the different gate layers, any two adjacent ones of the conductive structures having a spacing therebetween, and orthographic projections of upper ends of at least two of the conductive structures on a reference plane at least partially overlapping, and the reference plane being perpendicular to the second direction;
• and
• a periphery device electrically connected with the semiconductor structure.

A memory system, comprising:

• a three-dimensional (3D) memory comprising:
• a semiconductor structure comprising:
• a stack structure comprising gate layers and first dielectric layers disposed alternately;
• first gate isolation structures extending along a first direction and arranged at intervals along a second direction, the first gate isolation structures dividing the stack structure into at least one block comprising a memory region and a connection region that are distributed along the first direction, the first direction being perpendicular to the second direction;
• and
• conductive structures in the connection region, each conductive structure being electrically connected with one gate layer, and the different conductive structures being electrically connected with the different gate layers, any two adjacent ones of the conductive structures having a spacing therebetween, and orthographic projections of upper ends of at least two of the conductive structures on a reference plane at least partially overlapping, and the reference plane being perpendicular to the second direction;
• and
• a periphery device electrically connected with the semiconductor structure;
• and
• a controller electrically connected with the 3D memory to control the 3D memory to store data.