Semiconductor structure with backside metallization layers
AssigneeInternational Business Machines Corporation
InventorsRuilong Xie, Koichi Motoyama, Nicholas Anthony Lanzillo, Oleg Gluschenkov
Life of this patent
Estimating the term…
Abstract
A semiconductor structure includes a first metallization layer having a first plurality of metal containing lines, and a second metallization layer located above the first metallization layer. The second metallization layer includes a second plurality of metal containing lines. A first group of the second plurality of metal containing lines is disposed within the first metallization layer. The first group of the second plurality of metal containing lines is isolated from the first metallization layer by a dielectric barrier layer.
Claims20
A semiconductor structure, comprising:
- a first metallization layer comprising a first plurality of metal containing lines;
- and
- a second metallization layer located above the first metallization layer, wherein the second metallization layer comprises a second plurality of metal containing lines;
- wherein a first group of the second plurality of metal containing lines is disposed within the first metallization layer;
- and
- wherein the first group of the second plurality of metal containing lines is isolated from the first metallization layer by a dielectric barrier layer.
A semiconductor structure, comprising:
- a first metallization layer comprising a first plurality of metal containing lines in a first orientation;
- and
- a second metallization layer located above the first metallization layer, wherein the second metallization layer comprises a second plurality of metal containing lines in a second orientation;
- wherein the second plurality of metal containing lines comprises a first group of the second plurality of metal containing lines and a second group of the second plurality of metal containing lines;
- wherein the first group of the second plurality of metal containing lines is disposed within the first metallization layer and isolated from the first metallization layer by a dielectric barrier layer;
- and
- wherein at least one of the metal containing lines of the second group of the second plurality of metal containing lines is directly connected to at least one of the first plurality of metal containing lines.
An integrated circuit, comprising:
- one or more semiconductor structures, wherein at least one of the one or more semiconductor structures comprises:
- a first metallization layer comprising a first plurality of metal containing lines;
- and
- a second metallization layer located above the first metallization layer, wherein the second metallization layer comprises a second plurality of metal containing lines;
- wherein a first group of the second plurality of metal containing lines is disposed within the first metallization layer;
- and
- wherein the first group of the second plurality of metal containing lines is isolated from the first metallization layer by a dielectric barrier layer.
Dependencies are inferred from the claim text.