Substrate and semiconductor device including the same

A substrate, comprising:

• a first layer including a first power line extending in a first direction and that transmits a first voltage, and a second power line extending in the first direction and that transmits a second voltage;
• a second layer disposed under the first layer, wherein the second layer includes a third power line extending in a second direction different from the first direction, and a fourth power line extending in the second direction;
• a first via electrically connecting the first power line and the third power line to each other;
• a second via electrically connecting the second power line and the fourth power line to each other;
• a first bump disposed on an upper surface of the first layer and electrically connected to the first power line;
• and
• a second bump disposed on the upper surface of the first layer and electrically connected to the second power line,
• wherein the first layer further includes a fifth power line that transmits the first voltage,
• wherein the first power line, the second power line, and the fifth power line are sequentially arranged in a line along the first direction,
• wherein the first power line and the fifth power line are connected to each other via a connection line, wherein the connection line has a meandering shape bypassing the second power line,
• wherein the first power line is disposed on one side of the fifth power line, and a die-side capacitor is disposed on another side of the fifth power line,
• wherein the die-side capacitor is electrically connected to the first power line via the fifth power line and the connection line.

A semiconductor device, comprising:

• a board having a first area and a second area defined therein, wherein the first and second areas are distinct from each other;
• a semiconductor package disposed in the first area;
• and
• a power management chip disposed in the second area,
• wherein the semiconductor package operates using a first voltage and a second voltage different from the first voltage, and the power management chip operates using the first voltage,
• wherein the board includes:
• a first layer including a first power line extending in a first direction and a second power line extending in the first direction;
• a second layer disposed under the first layer and including a third power line extending in a second direction different from the first direction and a fourth power line extending in the second direction;
• a first via electrically connecting the first power line and the third power line to each other;
• and
• a second via electrically connecting the second power line and the fourth power line to each other,
• wherein the first voltage is transferred via the third power line, the first via, and the first power line, and the second voltage is transferred via the fourth power line, the second via, and the second power line.