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US 2024/0194555 A1Published application
Wafer dies with thermally conducting perimeter regions
AssigneeInternational Business Machines Corporation
InventorsMukta Ghate Farooq, Keiji Matsumoto, John Knickerbocker
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Abstract
A semiconductor structure includes a first back-end-of-line region coupled to a first side of a front-end-of-line region, a second back-end-of-line region coupled to a second side of the front-end-of-line region, and a thermally conducting region at least partially surrounding a perimeter of the front-end-of-line region, the first back-end-of-line region and the second back-end-of-line region.
Claims20
A semiconductor structure comprising:
- a first back-end-of-line region coupled to a first side of a front-end-of-line region;
- a second back-end-of-line region coupled to a second side of the front-end-of-line region;
- a thermally conducting region at least partially surrounding a perimeter of the front-end-of-line region, the first back-end-of-line region and the second back-end-of-line region.
A semiconductor structure comprising:
- a wafer die comprising a front-end-of-line region and a back-end-of-line region coupled to one side of the front-end-of-line region, the front-end-of-line region comprising one or more active devices;
- and
- a thermally conducting region at least partially surrounding a perimeter of the wafer die.
An integrated circuit comprising:
- a wafer die structure comprising:
- one or more active devices in a front-end-of-line region;
- a first back-end-of-line region coupled to a first side of the front-end-of-line region;
- and
- a second back-end-of-line region coupled to a second side of the front-end-of-line region;
- and
- a thermally conducting region at least partially surrounding a perimeter of the wafer die structure.
4 more elements
Dependencies are inferred from the claim text.