Semiconductor package and method for manufacturing the same

A semiconductor package, comprising:

• a first redistribution substrate;
• an internal package on the first redistribution substrate, the internal package including a first chip, a second chip that is hybrid bonded to the first chip, and a double gap-fill layer covering a side surface and a lower surface of the first chip;
• a sealant on the first redistribution substrate and sealing the internal package;
• a second redistribution substrate on the internal package and the sealant;
• and
• a first through-post extending through the sealant around the internal package and connecting the first redistribution substrate to the second redistribution substrate,
• wherein an area of a first horizontal plane of the first chip is smaller than an area of a second horizontal plane of the second chip, and
• wherein the double gap-fill layer covers an area corresponding to a difference between the area of the first horizontal plane and the area of the second horizontal plane.

A semiconductor package, comprising:

• a first chip including a first substrate, a first wiring layer on the first substrate, and through-electrodes passing through the first substrate and connected to the first wiring layer, the through-electrodes protruding from a lower surface of the first chip;
• a double gap-fill layer including a lower gap-fill layer covering the lower surface of the first chip and protruding portions of the through-electrodes, and an upper gap-fill layer covering a side surface of the first chip, the double gap-fill layer including an organic-inorganic composite material;
• a second chip on the first chip and the upper gap-fill layer, the second chip including a second wiring layer and a second substrate on the second wiring layer, the second chip being hybrid bonded to the first chip;
• a redistribution layer on a lower surface of the double gap-fill layer;
• and
• at least one bump on a lower surface of the redistribution layer and connected to the at least one of the through-electrodes through a redistribution line of the redistribution layer,
• wherein an area of the first chip in a first horizontal plane is smaller than an area of the second chip in a second horizontal plane, and
• wherein the double gap-fill layer covers an area corresponding to a difference between the area of the first chip in the first horizontal plane and the area of the second chip in the second horizontal plane.