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US 2024/0194552 A1Published application
Fan out package with integrated peripheral devices and methods
AssigneeIntel Corporation
InventorsLizabeth KESER, Bernd WAIDHAS, Thomas ORT, Thomas WAGNER
Life of this patent
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Abstract
A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.
Claims20
A semiconductor device, comprising:
- a first capacitor device having a top side and a bottom side, and a first sidewall and a second sidewall between the top side and the bottom side, the second sidewall opposite the first sidewall, and the first capacitor device having a lateral width between the first sidewall and the second sidewall;
- an encapsulant laterally adjacent to the first capacitor device, a first portion of the encapsulant in contact with the first sidewall of the first capacitor device, and a second portion of the encapsulant in contact with the second sidewall of the first capacitor device;
- a second capacitor device laterally spaced apart from the first capacitor device, the second capacitor device in contact with the encapsulant;
- an integrated routing layer comprising a plurality of successive dielectric layers and layers of electrical traces, the integrated routing layer on the top side of the first capacitor device, the integrated routing layer on the first portion of the encapsulant, the integrated routing layer on the second portion of the encapsulant, and the integrated routing layer including an electrical trace coupled to the top side of the first capacitor device, the electrical trace extending from a location vertically over the first capacitor device to a location laterally outside of the lateral width of the first capacitor device;
- a first solder ball coupled to the electrical trace of the integrated routing layer;
- and
- a second solder ball above and vertically overlapping with the second capacitor device.
4 more elements
A semiconductor device, comprising:
- a first passive device having a top side and a bottom side, and a first sidewall and a second sidewall between the top side and the bottom side, the second sidewall opposite the first sidewall, and the first passive device having a lateral width between the first sidewall and the second sidewall;
- a material for encapsulating the first passive device, the material laterally adjacent to the first passive device, a first portion of the material in contact with the first sidewall of the first passive device, and a second portion of the material in contact with the second sidewall of the first passive device;
- a second passive device laterally spaced apart from the first passive device, the second passive device in contact with the material for encapsulating the first passive device;
- a plurality of successive dielectric layers and layers of electrical traces, the plurality of successive dielectric layers and layers of electrical traces on the top side of the first passive device, the plurality of successive dielectric layers and layers of electrical traces on the first portion of the material, the plurality of successive dielectric layers and layers of electrical traces on the second portion of the material, and the plurality of successive dielectric layers and layers of electrical traces including an electrical trace coupled to the top side of the first passive device, the electrical trace extending from a location vertically over the first passive device to a location laterally outside of the lateral width of the first passive device;
- a conductive structure coupled to the electrical trace of the integrated routing layer;
- and
- a solder ball above and vertically overlapping with the second passive device.
4 more elements
A system, comprising:
- a motherboard;
- and
- a semiconductor device coupled to the motherboard, the semiconductor device comprising:
- a first capacitor device having a top side and a bottom side, and a first sidewall and a second sidewall between the top side and the bottom side, the second sidewall opposite the first sidewall, and the first capacitor device having a lateral width between the first sidewall and the second sidewall;
- an encapsulant laterally adjacent to the first capacitor device, a first portion of the encapsulant in contact with the first sidewall of the first capacitor device, and a second portion of the encapsulant in contact with the second sidewall of the first capacitor device;
- a second capacitor device laterally spaced apart from the first capacitor device, the second capacitor device in contact with the encapsulant;
- an integrated routing layer comprising a plurality of successive dielectric layers and layers of electrical traces, the integrated routing layer on the top side of the first capacitor device, the integrated routing layer on the first portion of the encapsulant, the integrated routing layer on the second portion of the encapsulant, and the integrated routing layer including an electrical trace coupled to the top side of the first capacitor device, the electrical trace extending from a location vertically over the first capacitor device to a location laterally outside of the lateral width of the first capacitor device;
- a first solder ball coupled to the electrical trace of the integrated routing layer;
- and
- a second solder ball above and vertically overlapping with the second capacitor device.
7 more elements
Dependencies are inferred from the claim text.