Apparatus and method for electroless surface finishing on glass
AssigneeIntel Corporation
InventorsKristof Darmawikarta, Steve S. Cho, Hiroki Tanaka, Haobo Chen, Gang Duan, Brandon Christian Marin, Suddhasattwa Nad, Srinivas V. Pietambaram
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Abstract
Apparatus and methods for electroless surface finishing on glass. A planarization process is performed on buildup dielectric and/or solder resist to create a flatter, more planar, upper surface for a substrate having a glass layer. Planarity is characterized by having surface variations of less than about 5 microns, as measured by recesses and/or protrusions. The planar surface enables finishing the substrate surface with an electroless NiPdAu process.
Claims20
An apparatus, comprising:
- a dielectric layer having an upper surface that is characterized by surface variations of less than plus or minus 5 microns;
- a glass core located under the dielectric layer;
- a conductive pillar located within the dielectric layer and oriented substantially perpendicular to the upper surface;
- a conductive dome attached to the conductive pillar at the upper surface, the conductive dome having a radius that exceeds a radius of the conductive pillar;
- a solder resist layer located on the upper surface;
- and
- an opening in the solder resist layer that is substantially centered on the conductive dome.
A substrate package, comprising:
- a substrate comprising:
- a glass core;
- a dielectric layer located on the glass core, the dielectric layer having an upper surface that is characterized by surface variations of less than plus or minus 5 microns;
- a conductive pillar located within the dielectric layer and oriented substantially perpendicular to the upper surface;
- a conductive dome, the conductive dome comprising nickel and attached to the conductive pillar, the conductive dome having a radius that exceeds a radius of the conductive pillar;
- a solder resist layer located on the upper surface;
- an opening in the solder resist layer that is substantially centered on the conductive dome;
- a solder material located in the opening in the solder resist and electrically connected to the conductive dome;
- and
- an integrated circuit die attached to the substrate via the solder material.
A method, comprising:
- fabricating a substrate having a dielectric layer comprising a conductive layer having a plurality of conductive contacts on a first surface;
- locating a pillar on at least one conductive contact of the plurality of conductive contacts;
- overlaying a dielectric layer above the first surface of the substrate;
- planarizing the dielectric layer to less than a plus or minus 5-micron surface variation;
- performing an electroless nickel electroless palladium immersion gold (ENEPIG) deposit on the at least one conductive contact;
- depositing and patterning solder resist over the planarized dielectric layer;
- and
- depositing solder material in an opening in the solder resist.
Dependencies are inferred from the claim text.