Integrated circuit device structures and double-sided electrical testing

A vertically stacked integrated circuit (IC) device structure, comprising:

• a field effect transistor (FET), comprising:
• a monocrystalline silicon body adjacent to an isolation dielectric;
• a gate stack adjacent to a sidewall of the body, the gate stack including a gate electrode separated from the sidewall by a gate dielectric;
• and
• a source and a drain coupled to the body on opposite sides of the gate stack;
• a front-side interconnect metallization layer over a front-side of the body and coupled to at least one of the source, drain, or gate electrode;
• and
• a thin film transistor (TFT), comprising:
• a channel material layer over a back-side surface of the body, opposite the front-side interconnect metallization layer, wherein the channel layer comprises a metal and a chalcogen or comprises a metal and oxygen;
• and
• a back-side device terminal electrically coupled to the channel material layer.

A method comprising;

• forming a field effect transistor (FET), comprising:
• a monocrystalline silicon body adjacent to an isolation dielectric;
• a gate stack adjacent to a sidewall of the body, the gate stack including a gate electrode separated from the sidewall by a gate dielectric;
• and
• a source and a drain coupled to the body on opposite sides of the gate stack;
• forming a front-side interconnect metallization layer over a front-side of the body and coupled to at least one of the source, drain, or gate electrode;
• removing a thickness of monocrystalline silicon material from a back side of the FET;
• forming a backside layer of semiconductor material over a back side of the FET, the backside layer of semiconductor material comprising an oxide semiconductor material, a metal chalcogenide material or a ferroelectric material;
• and
• forming a thin film transistor (TFT) or a non-volatile memory (NVM) device comprising the back-side semiconductor material.