Selective deposition of a protective layer to reduce interconnect structure critical dimensions

An integrated chip, comprising:

• an inter-level dielectric arranged over a substrate;
• an interconnect structure disposed within the inter-level dielectric, the interconnect structure comprising a lower sidewall and an upper sidewall over the lower sidewall;
• a dielectric layer arranged laterally between the lower sidewall and the inter-level dielectric, the interconnect structure extending below the dielectric layer;
• and
• wherein the interconnect structure is directly over the dielectric layer and a part of the inter-level dielectric, the part of the inter-level dielectric having a larger height than the dielectric layer in a first cross-sectional view.

An integrated chip, comprising:

• an inter-level dielectric arranged over a substrate;
• an interconnect structure disposed within the inter-level dielectric;
• a dimensional control layer arranged laterally between a lower part of the interconnect structure and the inter-level dielectric;
• and
• wherein the interconnect structure comprises a vertically extending surface that laterally contacts the inter-level dielectric over a first top surface of the dimensional control layer, as viewed in a first cross-sectional view.