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US 2024/0194480 A1Published application
Methods of Reducing Gate Spacer Loss During Semiconductor Manufacturing
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYi-Ruei JHAN, Han-Yu LIN, Li-Te LIN, Pinyen LIN
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Abstract
A method includes forming a dummy gate structure over a semiconductor substrate, forming a gate spacer over a sidewall of the dummy gate structure, performing a first implantation process to an upper portion of the gate spacer using a first dosage source, and performing a second implantation process to the upper portion of the gate spacer using a second dosage source including carbon. The second dosage source is different from the first dosage source.
Claims20
A method, comprising:
- forming a dummy gate structure over a semiconductor substrate;
- forming a gate spacer over a sidewall of the dummy gate structure;
- performing a first implantation process to an upper portion of the gate spacer using a first dosage source;
- and
- performing a second implantation process to the upper portion of the gate spacer using a second dosage source including carbon,
- wherein the second dosage source is different from the first dosage source.
3 more elements
A method, comprising:
- forming a semiconductor structure including a dummy gate structure disposed over a semiconductor substrate, the dummy gate structure extending lengthwise along a first direction;
- depositing a spacer layer over the dummy gate structure;
- recessing the spacer layer to form a gate spacer over a sidewall of the dummy gate structure, wherein the gate spacer includes an upper portion and a lower portion below the upper portion;
- performing a first implantation to the upper portion of the gate spacer to form a first treated upper portion using a first dosage source;
- and
- performing a second implantation to the first treated upper portion to form a second treated upper portion using a second dosage source including carbon,
- wherein the performing of the first implantation is tilted from a plane defined by the first direction and a second direction perpendicular to a top surface of the semiconductor substrate.
4 more elements
A semiconductor structure, comprising:
- a substrate;
- a metal gate structure disposed over the substrate;
- a first gate spacer disposed on a sidewall of the metal gate structure and including a first carbon concentration;
- a second gate spacer disposed on a sidewall of the first gate spacer, wherein the second gate spacer includes a bottom portion and a top portion above the bottom portion, wherein the top portion extends to a level below a top surface of the metal gate structure, wherein the top portion includes a second carbon concentration, and wherein the bottom portion includes a third carbon concentration smaller than the first carbon concentration and the second carbon concentration;
- a source/drain feature disposed adjacent to the second gate spacer;
- an etch stop layer (ESL) disposed on a sidewall of the second gate spacer and a top surface of the source/drain feature;
- and
- an interlayer dielectric (ILD) layer disposed between sidewalls of the ESL.
5 more elements
Dependencies are inferred from the claim text.