Memory Structure and Memory Device

A memory structure, comprising:

• a plurality of memory arrays arranged in parallel along a first direction and extending along a second direction,
• wherein a sensitivity amplifier array extending along the second direction is arranged between every two of the plurality of memory arrays, wherein the sensitivity amplifier array comprises an odd-numbered sensitivity amplifier array and an even-numbered sensitivity amplifier array, wherein the odd-numbered sensitivity amplifier array and the even-numbered sensitivity amplifier array are alternating along a first direction, and wherein the odd-numbered sensitivity amplifier array is connected to a plurality of odd-numbered global signal lines, and the even-numbered sensitivity amplifier array is connected to a plurality of even-numbered global signal lines;
• and
• spare memory arrays, arranged on one side of the plurality of memory arrays at an edge in the first direction, wherein a first sensitivity amplifier array is arranged between the memory arrays at the edge, and wherein the first sensitivity amplifier array is connected to the odd-numbered memory array;
• wherein both the plurality of odd-numbered global signal lines and the plurality of even-numbered global signal lines are connected.