Valley search scan bit line selection method to address memory hole and string process variation

A controller in communication with a memory apparatus including memory cells connected to one of a plurality of word lines and disposed in memory holes each coupled to one of a plurality of bit lines, the memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states, the controller configured to:

• for a group of the memory cells divided into a plurality of subsets, instruct the memory apparatus to determine whether comparatively fewer read errors of the memory cells arise while pre-charging ones of the plurality of bit lines associated with each of the plurality of subsets;
• and
• instruct the memory apparatus to pre-charge ones of the plurality of bit lines associated with one the plurality of subsets with comparatively fewer read errors and read the memory cells associated therewith during a scan operation.

A method of operating a memory apparatus including memory cells connected to one of a plurality of word lines and disposed in memory holes each coupled to one of a plurality of bit lines, the memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states, the method comprising the steps of:

• for a group of the memory cells divided into a plurality of subsets, determining whether comparatively fewer read errors of the memory cells arise while pre-charging ones of the plurality of bit lines associated with each of the plurality of subsets;
• and
• pre-charging ones of the plurality of bit lines associated with one the plurality of subsets with comparatively fewer read errors and reading the memory cells associated therewith during a scan operation.