Architecture and method for nand memory programming
AssigneeYangtze Memory Technologies Co., Ltd.
InventorWeijun WAN
Life of this patent
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Abstract
A method for operating a memory device is disclosed. An inhibit information is set to a first latch. An first programming voltage is applied to word lines of memory cells to program the memory cells. The inhibit information in the first latch is inverted to form a first information. A verification operation is applied on the memory cells, and a second information is stored in the first latch according to the first information and the verification operation. After the verification operation, the second information is inverted in the first latch.
Claims20
A method for operating a memory device, comprising:
- setting an inhibit information to a first latch;
- applying a first programming voltage to word lines of memory cells to program the memory cells;
- inverting the inhibit information in the first latch to form a first information;
- performing a verification operation on the memory cells, and storing a second information in the first latch according to the first information and the verification operation;
- and
- after the verification operation, inverting the second information in the first latch.
A memory device, comprising:
- a memory array comprising memory cells;
- and
- a peripheral circuit coupled to the memory array, wherein the peripheral circuit is configured to:
- set an inhibit information to a first latch;
- apply a first programming voltage to word lines of memory cells to program the memory cells;
- invert the inhibit information in the first latch to form a first information;
- perform a verification operation on the memory cells, and store a second information in the first latch according to the first information and the verification operation;
- and
- after the verification operation, invert the second information in the first latch.
A memory system, comprising:
- a memory device comprising:
- a memory array comprising memory cells;
- and
- a peripheral circuit coupled to the memory array and configured to:
- sett an inhibit information to a first latch;
- apply a first programming voltage to word lines of memory cells to program the memory cells;
- invert the inhibit information in the first latch to form a first information;
- perform a verification operation on the memory cells, and store a second information in the first latch according to the first information and the verification operation;
- and
- after the verification operation, invert the second information in the first latch;
- and
- a controller coupled to the memory device.
Dependencies are inferred from the claim text.