Memory device and operating method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsYonghyuk Choi, Jaeduk Yu, Yohan Lee
Life of this patent
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Abstract
A memory device includes a word line area that is between a bit line and a common source line. The word line area includes a plurality of stacks. A first area includes first stacks with a first resistance value in the word line area, a second area includes second stacks with a second resistance value in the word line area, wherein the second resistance value is different from the first resistance value, a third area includes third stacks with a third resistance value that different from the first resistance value, and a processor is configured to control a recovery sequence of the first area, the second area, and the third area.
Claims20
A memory device, comprising:
- a word line area between a bit line and a common source line, the word line area comprising a plurality of stacks including first, second, and third stacks;
- a first area comprising the first stacks with a first resistance value in the word line area;
- a second area comprising the second stacks with a second resistance value in the word line area, wherein the second resistance value is different from the first resistance value;
- and
- a third area comprising the third stacks with a third resistance value that different from the first resistance value in the word line area;
- and
- a processor configured to control a recovery sequence of the first area, the second area, and the third area,
- wherein the processor is configured to perform a first recovery operation for the first area starting at a first point in time, and
- wherein the processor is configured to perform a second recovery operation for the second area and a third recovery operation for the third area starting at or after a second point in time that is different from the first point in time.
An operating method of a memory device for recovering a word line area that is between a bit line and a common source line and includes a plurality of stacks comprising first, second, and third stacks, the operating method comprising:
- performing a first recovery operation for a first area in the word line area comprising the first stacks starting at a first point in time;
- and
- performing a second recovery operation for a second area in the word line area comprising the second stacks and a third recovery operation for a third area in the word line area comprising the third stacks starting at or after a second point in time that is different from the first point in time.
A memory device, comprising:
- a word line area that is between a bit line and a common source line, the word line area comprising a plurality of stacks including first, second, and third stacks,
- a first area comprising the first stacks with a first resistance value in the word line area;
- a second area comprising the second stacks with a second resistance value in the word line area, wherein the second resistance value is different from the first resistance value;
- and
- a third area comprising the third stacks with a third resistance value that is different from the first resistance value in the word line area,
- wherein the memory device is configured to perform a first recovery operation for the first area starting at a first point in time, and
- wherein the memory device is configured to perform at least one of a second recovery operation for the second area or a third recovery operation for the third area starting at a second point in time that is different from the first point in time.
Dependencies are inferred from the claim text.