Memory cells and memory array structures and methods of their fabrication

A memory, comprising:

• a plurality of data lines;
• a common source;
• an array of memory cells comprising a plurality of strings of series-connected memory cells each selectively connected to a respective data line of the plurality of data lines and each selectively connected to the common source;
• and
• a controller for access of the array of memory cells;
• wherein at least one memory cell of a particular string of series-connected memory cells of the plurality of strings of series-connected memory cells comprises:
• a control gate;
• a channel;
• a gate dielectric between the channel and the control gate;
• a charge-storage node between the gate dielectric and the control gate;
• a charge-blocking material between the charge-storage node and the control gate;
• a laminated dielectric between the charge-blocking material and the control gate;
• and
• a high-K dielectric between the laminated dielectric and the control gate;
• wherein the laminated dielectric comprises an instance of a first dielectric material between the charge-blocking material and the high-K dielectric, and an instance of a second dielectric material between the instance of the first dielectric material and the high-K dielectric;
• and
• wherein the instance of the first dielectric material has a higher oxygen areal density than an oxygen areal density of the instance of the second dielectric material.

A memory array structure, comprising:

• a data line;
• a common source;
• and
• a channel-material structure between the data line and the common source;
• a control gate surrounding the channel-material structure;
• a laminated dielectric between the channel-material structure and the control gate;
• and
• a high-K dielectric between the laminated dielectric and the control gate;
• wherein the channel-material structure comprises:
• a channel material electrically connected to the common source and electrically connected to the data line;
• a gate dielectric between the channel material and the control gate;
• a charge-storage node between the gate dielectric and the control gate;
• and
• a charge-blocking material between the charge-storage node and the control gate;
• wherein the laminated dielectric comprises an instance of a first dielectric material between the channel-material structure and the high-K dielectric, and an instance of a second dielectric material between the instance of the first dielectric material and the high-K dielectric;
• and
• wherein the instance of the first dielectric material has a higher oxygen areal density than an oxygen areal density of the instance of the second dielectric material.