US 2024/0194261 A1 · SEMICONDUCTOR MEMORY DEVICE

Abstract

A semiconductor memory device includes a source bonding structure including a first source layer and a second source layer bonded to each other, a first memory cell array structure connected to the first source layer of the source bonding structure, and a second memory cell array structure connected to the second source layer of the source bonding structure. The source bonding structure includes at least one of a semiconductor bonding area and a metal bonding area.

Claims14

Dependent claims

A semiconductor memory device comprising:

a source bonding structure including a first source layer and a second source layer bonded to each other;
a first memory cell array structure connected to the first source layer of the source bonding structure;
and
a second memory cell array structure connected to the second source layer of the source bonding structure,
wherein the source bonding structure includes a semiconductor bonding area and a metal bonding area.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/331,821Filed 8 Jun 2023

Priority

KR 10-2022-01694597 Dec 2022

Published

13 Jun 2024

Term ends

Not estimatedThe source records don’t support an estimate.

Classification18 codes

G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
H10B 41/10
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/40
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the peripheral circuit region

Abstract

Facts

Application

18/331,821Filed 8 Jun 2023

Priority

KR 10-2022-01694597 Dec 2022

Published

13 Jun 2024

Term ends

Not estimatedThe source records don’t support an estimate.

Classification18 codes

G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
H10B 41/10
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/40
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the peripheral circuit region

Semiconductor memory device

Life of this patent

Abstract

Claims14

Semiconductor memory device

Life of this patent

Abstract

Claims14