A method for manufacturing a semiconductor-element-containing memory device that includes a first memory cell configured to perform a data write operation, a data read operation, and a data erase operation by using a voltage that is applied to a first wiring layer, a second wiring layer, and a third wiring layer, the first wiring layer being connected to a first impurity layer, the second wiring layer being connected to a first gate conductor layer, a second gate conductor layer, and a second impurity layer, the third wiring layer being connected to a third gate conductor layer, a fourth gate conductor layer, and a third impurity layer, the method comprising the steps of:
- forming the first impurity layer over a substrate and forming, over the first impurity layer, in a layered manner, a first insulating layer, a first material layer, a second insulating layer, a second material layer, a third insulating layer, a third material layer, a fourth insulating layer, a fourth material layer, a fifth insulating layer, a fifth material layer, and a sixth insulating layer, which are disposed in this order, starting from a lower position;
- forming a first hole extending through the first to sixth insulating layers and the first to fifth material layers in a vertical direction and having a bottom portion in the first impurity layer;
- filling the first hole with a first pillar-shaped semiconductor layer;
- removing the third material layer to form a first space;
- forming a first semiconductor layer in contact with an inner wall of the first space with a portion of the first space being left unfilled, the first semiconductor layer containing a donor impurity or an acceptor impurity;
- forming a first alloy layer that is made of an alloy or a metal and fills the portion of the first space that is inside the first semiconductor layer:
- performing a heat treatment, thereby causing the first semiconductor layer and the first alloy layer to be integrated with each other to form a second alloy layer and also causing the donor impurity or the acceptor impurity of the first semiconductor layer to diffuse into the first pillar-shaped semiconductor layer to form the second impurity layer;
- removing the first material layer, the second material layer, the fourth material layer, and the fifth material layer to form a second space and forming a first gate insulating layer that covers at least an exposed portion of a side surface of the first pillar-shaped semiconductor layer in the second space;
- forming a first conductor layer, a second conductor layer, a third conductor layer, and fourth conductor layer, which are disposed in this order, starting from a lower position, and fill the second space;
- etching, with a single mask, the second alloy layer, the first to fourth conductor layers, and the second to sixth insulating layers to form the first to fourth gate conductor layers and the second wiring layer such that the first to fourth gate conductor layers and the second wiring layer have substantially a same shape as viewed in plan view;
- forming the third impurity layer on a top portion of the first pillar-shaped semiconductor layer;
- and
- forming the third wiring layer that is connected to the third impurity layer, the third wiring layer extending in a same direction as the first wiring layer and being perpendicular to the second wiring layer, as viewed in plan view.