Apparatuses and methods for logic/memory devices
AssigneeLodestar Licensing Group LLC
InventorRichard C. Murphy
Life of this patent
Estimating the term…
Abstract
Apparatuses and methods are provided for logic/memory devices. An example apparatus comprises a plurality of memory components adjacent to and coupled to one another. A logic component is coupled to the plurality of memory components. At least one memory component comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component. Timing circuitry is coupled to the array and sensing circuitry and configured to control timing of operations for the sensing circuitry. The logic component comprises control logic coupled to the timing circuitry. The control logic is configured to execute instructions to cause the sensing circuitry to perform the operations.
Claims20
An apparatus, comprising:
- a logic component;
- and
- a plurality of memory components coupled with the logic component via one or more through silicon vias (TSVs);
- wherein a respective memory component of the plurality of memory components comprises:
- timing circuitry;
- an array of memory cells of a bank of the respective memory component;
- circuitry of the respective memory component, the circuitry coupled to the array and configured to perform one or more logical operations using data stored in the array of memory cells;
- wherein the logic component comprises:
- a first control logic coupled to a first group of partitioned banks of the plurality of memory components, wherein at least two partitioned banks of the first group are on different memory components;
- and
- a second control logic coupled to a second group of partitioned banks of the plurality of memory components.
A system, comprising:
- a logic component;
- and
- a plurality of memory components coupled with the logic component;
- wherein a respective memory component of the plurality of memory components comprises:
- an array of memory cells of a bank of the respective memory component;
- circuitry of the respective memory component, the circuitry coupled to the array and configured to perform one or more logical operations using data stored in the array of memory cells;
- and
- a sequencer configured to cause the circuitry to perform the one or more logical operations;
- wherein the logic component comprises:
- a first control logic coupled to a first group of partitioned banks of the plurality of memory components;
- and
- a second control logic coupled to a second group of partitioned banks of the plurality of memory components.
An apparatus, comprising:
- a logic component;
- and
- a plurality of memory components coupled with the logic component;
- wherein a respective memory component of the plurality of memory components comprises:
- an array of memory cells of a bank of the respective memory component;
- wherein the logic component comprises:
- a first control logic coupled to one or more first portions of the plurality of memory components, the first control logic configured to operate on a reduced instruction set computer (RISC) type instruction and to further cause performance of the one or more logical operations using data stored in the respective array of memory cells and corresponding to processing in memory (PIM) operations;
- and
- a second control logic coupled to one or more second portions of the plurality of memory components, the second control logic configured to operate on a RISC type instruction and to further cause performance of one or more logical operations using data stored in the respective array of memory cells and corresponding to PIM operations.
Dependencies are inferred from the claim text.