Method for controlling nand flash memory to implement xnor operation

A method for controlling a NAND flash memory to implement an XNOR operation, comprising the following steps:

• S0:
• providing a NAND flash memory, wherein the NAND flash memory comprises at least one first memory block, at least one second memory block, and multiple sense amplifiers, the first memory block comprises multiple first synaptic strings, multiple first bit lines, and multiple first word lines, each of the first synaptic strings comprises a first drain selector and a first memory module connected in series, the first memory module comprises multiple first memory cells connected in series, the first synaptic strings are connected to the first bit lines in a one-to-one correspondence manner, the first word lines are connected to all the first memory cells, the second memory block comprises multiple second synaptic strings, multiple second bit lines, and multiple second word lines, each of the second synaptic strings comprises a second drain selector and a second memory module connected in series, the second memory module comprises multiple second memory cells connected in series, the second synaptic strings are connected to the second bit lines in a one-to-one correspondence manner, the second word lines are connected to all the second memory cells, and the first word lines and the second word lines are connected to the sense amplifiers in a one-to-one correspondence manner;
• S1:
• taking the first synaptic string and the second synaptic string connected to a common one of the sense amplifiers as associated synaptic strings, taking any one of the first memory cells of the first synaptic string used as the associated synaptic string as a first memory cell to be used, taking any one of the second memory cells of the second synaptic string used as the associated synaptic string as a second memory cell to be used, writing first data into the first memory cell to be used, and writing second data into the second memory cell to be used, wherein the first data and the second data are mutually inverted data;
• S2:
• taking the remaining first memory cells of the first synaptic string used as the associated synaptic string as third memory cell or third memory cells to be used, taking the remaining second memory cells of the second synaptic string used as the associated synaptic string as fourth memory cell or fourth memory cells to be used, writing third data into part or all of the third memory cell or third memory cells to be used, and writing fourth data into part or all of the fourth memory cell or fourth memory cells to be used;
• S3:
• applying a first potential voltage to a corresponding one of the first word lines connected to the first memory cell to be used, applying a second potential voltage to a corresponding one of the second word lines connected to the second memory cell to be used, applying a third potential voltage to the first drain selector, applying a fourth potential voltage to the second drain selector, applying a fifth potential voltage to a corresponding one of the first word lines connected to the third memory cell or third memory cells to be used in which the third data is written, applying a sixth potential voltage to a corresponding one of the second word lines connected to the fourth memory cell or fourth memory cells to be used in which the fourth data is written, and applying a seventh potential voltage to a corresponding one of the first word lines connected to the third memory cell or third memory cells to be used that do not store data and a corresponding one of the second word lines connected to the fourth memory cell or fourth memory cells to be used that do not store data;
• and
• S4:
• reading the data from the first synaptic string and the second synaptic string used as the associated synaptic strings by the corresponding one of the sense amplifiers.