Nonvolatile memory devices

A nonvolatile memory device comprising:

• a memory cell region including a first metal pad;
• a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad;
• a memory cell array in the memory cell region, the memory cell array including a plurality of mats corresponding to different word-lines, each of the plurality of mats including a plurality of cell strings perpendicular to a substrate respectively, wherein:
• a first cell string of a first mat of the plurality of mats is connected to a plurality of first word-lines, a first bit-line, a first string selection line and a first ground selection line,
• a second cell string of a second mat of the plurality of mats is connected to a plurality of second word-lines, a second bit-line, a second string selection line and a second ground selection line, and
• each of the first and second cell strings includes at least one ground selection transistor, a plurality of memory cells, and a plurality of string selection transistors coupled in series;
• a row decoder in the peripheral circuit region, the row decoder configured to apply a first voltage to a third word-line among the plurality of first and second word-lines through the first metal pad and the second metal pad when a memory operation of the nonvolatile memory device is performed for only one of the first and second mats in a single mat mode and to apply a second voltage greater than the first voltage to the third word-line through the first metal pad and the second metal pad when the memory operation is performed for both of the first and second mats simultaneously in a multi-mat mode;
• and
• a control circuit in the peripheral circuit region, the control circuit configured to control the row decoder based on a command and an address from an outside of the nonvolatile memory device.

A method of operating a nonvolatile memory device including a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array in the memory cell region, the memory cell array including a plurality of mats corresponding to different word-lines, each of the plurality of mats including a plurality of cell strings perpendicular to a substrate respectively, a first cell string of a first mat of the plurality of mats connected to a plurality of first word-lines, a first bit-line, a first string selection line and a first ground selection line, a second cell string of a second mat of the plurality of mats connected to a plurality of second word-lines, a second bit-line, a second string selection line and a second ground selection line, each of the first and second cell strings including at least one ground selection transistor, a plurality of memory cells, and a plurality of string selection transistors coupled in series, the method comprising:

• applying, by a row decoder in the peripheral circuit region, a first voltage or a second voltage to a third word-line among the plurality of first and second word-lines through the first and second metal pads based on whether a program operation of the nonvolatile memory device is performed for only one of the first and second mats or whether the program operation is performed for both of the first and second mats simultaneously.