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US 2024/0194236 A1Published application
Negative capacitance for ferroelectric capacitive memory cell
AssigneeInternational Business Machines Corporation
InventorsTakashi Ando, Reinaldo Vega, David Wolpert, Nicholas Anthony Lanzillo
Life of this patent
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Abstract
A capacitive memory cell includes an electrode, a tunneling barrier layer in direct contact with the electrode, a charge trapping layer in direct contact with the tunneling barrier layer, a ferroelectric layer in direct contact with the charge trapping layer, and another electrode in direct contact with the ferroelectric layer.
Claims20
A capacitive memory cell comprising:
- a first electrode;
- a tunneling barrier layer in direct contact with the first electrode;
- a charge trapping layer in direct contact with the tunneling barrier layer;
- a ferroelectric layer in direct contact with the charge trapping layer;
- and
- a second electrode in direct contact with the ferroelectric layer.
3 more elements
An integrated circuit comprising:
- a charging transistor;
- a capacitive memory cell connected to the charging transistor and comprising:
- a first electrode;
- a tunneling barrier layer;
- a charge trapping layer;
- a ferroelectric layer;
- and
- a second electrode;
- a discharging transistor connected to the capacitive memory cell;
- and
- a sensing component configured to measure a discharge of the capacitive memory cell.
8 more elements
A method of operating a capacitive memory cell, the method comprising:
- applying an electrical bias to a first electrode to cause electrons to migrate from a second electrode, through a tunneling barrier layer, into a charge trapping layer;
- removing the electrical bias to store a memory state;
- and
- sensing the memory state with a sensing circuit.
1 more element
Dependencies are inferred from the claim text.