Memory device including memory package and memory system including the memory device
AssigneeSK hynix Inc.
InventorsSung Geun KANG, In Bo SHIM, Su Il JIN, Eun Kyu CHOI
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Abstract
A memory system includes a memory device and a memory controller for providing data to the memory device based on a clock signal. The memory device includes a first memory group; a second memory group; an internal clock generator for generating a first internal clock signal and a second internal clock signal, which respectively correspond to a first period and a second period of the clock signal; and a data distributor for providing the data respectively to the first memory group and the second memory group, based on the first internal clock signal and the second internal clock signal.
Claims20
A memory system comprising:
- a memory device;
- and
- a memory controller configured to provide data to the memory device based on a clock signal,
- wherein the memory device includes:
- a first memory group;
- a second memory group;
- an internal clock generator configured to generate a first internal clock signal and a second internal clock signal, which respectively correspond to a first period and a second period of the clock signal;
- and
- a data distributor configured to provide the data respectively to the first memory group and the second memory group, based on the first internal clock signal and the second internal clock signal.
A memory system comprising:
- a memory device;
- and
- a memory controller configured to provide data to the memory device based on a clock signal,
- wherein the memory device includes:
- first to nth memory groups each including a plurality of memory dies;
- an internal clock generator configured to generate first to nth internal clock signals respectively corresponding to the first to nth memory groups, based on the clock signal;
- and
- a data distributor configured to provide the data to the first to nth memory groups, respectively, based on the first to nth internal clock signals.
A memory package comprising:
- first to nth memory groups each including a plurality of memory dies;
- an internal clock generator configured to generate first to nth internal clock signals, provide the first to nth internal clock signals to the first to nth memory groups, respectively, based on a clock signal;
- and
- a data distributor configured to receive data, and distribute the data to the first to nth memory groups according to the clock signal, respectively, based on the first to nth internal clock signals.
Dependencies are inferred from the claim text.