Scanning signal line drive circuit and display device provided with same

A scanning signal line drive circuit configured to drive a plurality of scanning signal lines, the scanning signal line drive circuit comprising:

• a shift register configured to operate based on a plurality of clock signals and including a plurality of stages corresponding to the plurality of scanning signal lines on a one-to-one basis, wherein
• a unit circuit constituting each of the plurality of stages included in the shift register includes
• a first node,
• a second node,
• a third node,
• a first output node configured to output an output signal to a corresponding one of the plurality of scanning signal lines,
• a first output control transistor including a control terminal connected to the first node, a first conduction terminal applied with one of the plurality of clock signals, and a second conduction terminal connected to the first output node,
• a first node pull-up unit configured to change a potential of the first node toward an on level, based on a set signal,
• a first node pull-down unit configured to change the potential of the first node toward an off level, based on a reset signal,
• a stabilization transistor including a control terminal connected to the second node, a first conduction terminal connected to the first node or the first output node, and a second conduction terminal applied with an off level potential, and
• a stabilization circuit connected to the second node,
• the stabilization circuit includes
• a second node pull-up transistor including a control terminal connected to the third node, a first conduction terminal applied with one of the plurality of clock signals, and a second conduction terminal connected to the second node,
• a first second node pull-down transistor including a control terminal connected to the first node, a first conduction terminal connected to the second node, and a second conduction terminal applied with an off level potential,
• a first third node pull-down transistor including a control terminal connected to the first node, a first conduction terminal connected to the third node, and a second conduction terminal applied with an off level potential,
• a third node pull-up transistor including a control terminal and a first conduction terminal that are applied with one of the plurality of clock signals and including a second conduction terminal connected to the third node, and
• a second third node pull-down transistor including a control terminal applied with one of the plurality of clock signals, a first conduction terminal connected to the third node, and a second conduction terminal applied with an off level potential, and
• a clock signal applied to the control terminal of the second third node pull-down transistor changes from the off level to the on level at a timing when a clock signal applied to the control terminal of the third node pull-up transistor changes from the on level to the off level.