Graphics processor

A tiled-based graphics processor comprising:

• a plurality of tiling units operable to sort geometry to be processed to generate a render output into primitive listing regions that the render output is divided into;
• and
• an assigning circuit configured to, for each of one or more initial regions of a set of initial regions that a render output is divided into, and into which geometry to be processed to generate the render output is sorted, and wherein each initial region of the set of initial regions encompasses plural primitive listing regions:
• assign a tiling unit of the plurality of tiling units to sort geometry for the respective initial region into primitive listing regions that the respective initial region encompasses;
• and
• cause the assigned tiling unit to sort the geometry for the respective initial region into the primitive listing regions that the respective initial region encompasses.

A non-transitory computer readable storage medium storing software code which when executing on a processor performs a method of operating a tiled-based graphics processor that comprises a plurality of tiling units operable to sort geometry to be processed to generate a render output into primitive listing regions that the render output is divided into;

• the method comprising:
• sorting geometry to be processed to generate a render output into a set of initial regions that the render output is divided into, wherein each initial region of the set of initial regions encompasses plural primitive listing regions;
• and
• for each of one or more initial regions of the set of initial regions:
• assigning a tiling unit of the plurality of tiling units to sort geometry for the respective initial region into primitive listing regions that the respective initial region encompasses;
• and
• the assigned tiling unit sorting the geometry for the respective initial region into the primitive listing regions that the respective initial region encompasses.