Method of analyzing electrostatic discharge network using common resistance removal, system performing the same and method of manufacturing semiconductor device using the same

A system of analyzing an electrostatic discharge (ESD) network, the system comprising:

• a storage device configured to store information including procedures of a semiconductor device;
• and
• a processor configured to access the storage device, and to execute the procedures to:
• receive input data characterizing the semiconductor device, the semiconductor device including an input/output (I/O) pad, an ESD protection circuit, and at least one functional circuit;
• calculate, based on the input data, a common resistance of the ESD protection circuit using a plurality of resistances and at least one predetermined equation, the plurality of resistances associated with the I/O pad, the ESD protection circuit, and the at least one functional circuit;
• and
• perform a network analysis on the semiconductor device by excluding the common resistance.

A method of analyzing an electrostatic discharge (ESD) network, the method comprising:

• receiving input data characterizing a semiconductor device, the semiconductor device including an input/output (I/O) pad, an ESD protection circuit, and at least one functional circuit that are connected through a first node;
• obtaining a first resistance, a second resistance, and a third resistance associated with the I/O pad, the ESD protection circuit, and the at least one functional circuit;
• calculating, based on the input data, a common resistance of the ESD protection circuit using the first resistance, the second resistance, the third resistance, and at least one predetermined equation;
• and
• performing a network analysis on the semiconductor device, wherein performing the network analysis comprises removing the common resistance from the semiconductor device, performing a simulation on the semiconductor device from which the common resistance is removed, and checking, based on a result of the simulation, whether a predetermined rule is violated,
• wherein the ESD protection circuit includes:
• a first diode and a second resistor connected in series between a power supply voltage and the first node;
• and
• a second diode and a third resistor connected in series between the first node and a ground voltage,
• wherein the first resistance corresponds to a resistance between the I/O pad and the first diode in the ESD protection circuit, the second resistance corresponds to a resistance between the I/O pad and the second diode in the ESD protection circuit, and the third resistance corresponds to a resistance between the first diode and the second diode in the ESD protection circuit, and
• wherein a first value is obtained by adding the first resistance and the second resistance, a second value is obtained by subtracting the third resistance from the first value, and the common resistance is obtained by dividing the second value by two.