Automatic test pattern generation to increase coverage in detecting defects in analog circuits

A system comprising:

• a memory storing instructions;
• and
• a processing device, coupled with the memory and to execute the instructions, the instructions when executed cause the processing device to:
• receive a description of an analog circuit and a specification of a defect that may occur in the analog circuit;
• apply multiple iterations of a strategy to update a test pattern to detect the defect, wherein each iteration comprises:
• determining nominal responses and defect responses of the analog circuit to trial test patterns that are based on a current candidate test pattern;
• wherein the nominal response is a response of the analog circuit without the specified defect, and the defect response is a response of the analog circuit with the specified defect;
• and
• updating the current candidate test pattern based on the differences between the nominal responses and the defect responses for the trial test patterns.

A non-transitory computer readable medium comprising stored instructions, which when executed by a processing device, cause the processing device to:

• receive a description of an analog circuit and a specification of a defect that may occur in the analog circuit;
• perform alternating current (AC) simulations of the analog circuit to determine nominal responses and defect responses of the analog circuit to trial test patterns;
• wherein the nominal response is a response of the analog circuit without the specified defect, and the defect response is a response of the analog circuit with the specified defect;
• and
• select one or more of the trial test patterns based on differences between the nominal responses and the defect responses for the trial test patterns.