US 2024/0193228 A1 · METHOD FOR MAPPING AN INPUT VECTOR TO AN OUTPUT VECTOR BY MEANS OF A MATRIX CIRCUIT

Abstract

The disclosure relates to a method for mapping an input vector to an output vector by means of a matrix circuit which has memory cells arranged in a matrix in a plurality of rows and a plurality of columns and first, second and third lines, each memory cell having an adjustable memory state, is connected to the first line (22) of the corresponding row, is connected to the second and third lines of the corresponding column and is set up to generate an electrical current (I1, I2, I3) depending on the memory state and voltages applied to the first, second and third lines, is connected to the second and third lines of the corresponding column and is arranged to conduct an electric current (I1, I2, I3) into the third line (26) as a function of the memory state and voltages applied to the first, second and third lines, each memory cell having a semiconductor switching element (28) with a control terminal which is connected to the second line (24) of the corresponding column; wherein input voltages (U1, U2, U3) corresponding to components of the input vector are applied (110) to the first lines; wherein for each column: a ramp voltage (V1, V2, V3) is applied (120) to the second line assigned to the column, the level of which is increased with time (130); a total current is detected at the third line assigned to the column and a time period elapsed since a start time of the level increase of the corresponding ramp voltage is determined (150) until the magnitude of the total current reaches a certain current magnitude threshold (Ig) (140); and a component of the output vector corresponding to the column is determined (170) based on the elapsed time period (t1, t2, t3).

Claims15

Dependent claims

A method for mapping an input vector to an output vector by means of a matrix circuit which has memory cells and first, second and third lines arranged in a matrix in a plurality of rows and a plurality of columns, one of the first lines (22) being assigned to each row and one of the second and one of the third lines (24, 26) being assigned to each column,

wherein each memory cell has an adjustable memory state,
wherein each memory cell is connected to the first line (22) assigned to the row in which the memory cell is located and to the second and third lines (24, 26) assigned to the column in which the memory cell is located,
wherein each memory cell is arranged to conduct an electric current (I1, I2, I3) from the first to the third line (26) as a function of the memory state and of voltages applied to the first, the second and the third line,
wherein each memory cell comprises a semiconductor switching element (28) having a control terminal connected to the second line (24) assigned to the column in which the semiconductor switching element is located;
wherein input voltages (U1, U2, U3) corresponding to components of the input vector are applied to the first lines (110);
the method comprising for each column:
applying (120) a ramp voltage (V1, V2, V3) to the second line assigned to the column,
increasing (130) the level of the ramp voltage over time;
detecting a total current at the third line assigned to the column;
determining (150) a time period that has elapsed from a start time of the level increase of the corresponding ramp voltage until a certain current magnitude threshold (Ig) is reached (140) by the magnitude of the total current;
and
determining (170) a component of the output vector corresponding to the column based on the elapsed time period (t1, t2, t3).

9 more elements

A circuit comprising

a matrix circuit which has memory cells and first, second and third lines arranged in a matrix in a plurality of rows and a plurality of columns, one of the first lines (22) being assigned to each row and one of the second and one of the third lines (24, 26) being assigned to each column,
wherein each memory cell has an adjustable memory state,
wherein each memory cell is connected to the first line (22) assigned to the row in which the memory cell is located and to the second and third lines (24, 26) assigned to the column in which the memory cell is located,
wherein each memory cell is arranged to conduct an electric current (I1, I2, I3) from the first to the third line (26) as a function of the memory state and of voltages applied to the first, the second and the third line,
wherein each memory cell comprises a semiconductor switching element (28) having a control terminal connected to the second line (24) assigned to the column in which the semiconductor switching element is located;
and
a controller configured to
apply (120) a ramp voltage (V1, V2, V3) to the second line assigned to the column,
increase (130) the level of the ramp voltage over time;
detect a total current at the third line assigned to the column;
determine (150) a time period that has elapsed from a start time of the level increase of the corresponding ramp voltage until a certain current magnitude threshold (Ig) is reached (140) by the magnitude of the total current;
and
determine (170) a component of the output vector corresponding to the column based on the elapsed time period (t1, t2, t3).

10 more elements

Dependencies are inferred from the claim text.

Method for mapping an input vector to an output vector by means of a matrix circuit

Life of this patent

Method for mapping an input vector to an output vector by means of a matrix circuit

Life of this patent

Abstract

Claims15