Compression of sparse matrices for vector processing

A circuit arrangement comprising:

• first register circuitry configured to store t elements of an input vector;
• a control circuit configured to input:
• a sequence of one or more value vectors, each value vector having s elements of a partition of a plurality of partitions of an m×n matrix, wherein the partition has s rows and t columns, each element of the value vector corresponds to a row of the partition, and s<m and t<n, and
• a sequence of one or more column-index vectors, each column-index vector associated with a value vector in the sequence of one or more value vectors and each column-index vector having s elements associated with the s elements of the associated value vector, respectively;
• a selection circuit configured to select s elements in parallel from the first register circuitry in response to values of the s elements of and in-process column-index vector of the sequence of one or more column-index vectors;
• a plurality of s multiplication circuits configured to generate s products in parallel from the s elements selected from the first register circuitry and the s elements of the value vector associated with the in-process column-index vector;
• and
• a plurality of s accumulation circuits configured to accumulate s sums in parallel from the s products, respectively, wherein each sum of the s sums is a sum of the products generated in response to like-indexed elements in the sequence of one or more value vectors and like-indexed elements in the sequence of column-index vectors.

A circuit arrangement comprising:

• a plurality of vector processors configured to multiply a compressed sparse matrix by an input vector having n elements, wherein the compressed sparse matrix represents an m×n sparse matrix and the compressed sparse matrix includes for one or more partitions of a plurality of partitions of the sparse matrix, a respective sequence of one or more value vectors and one or more associated column index vectors, wherein each value vector has s elements of a partition of the plurality of partitions, each column-index vector has s elements associated with the s elements of the associated value vector, respectively, elements of each value vector correspond to rows of the partition, each partition has elements of a group of s rows and t columns of the sparse matrix, and s<m and t<n;
• wherein each vector processor is configured to generate in parallel for a partition of the plurality of partitions:
• s products of elements of a value vector of the one or more value vectors and elements selected from t elements of the input vector according to column index values in the associated column-index vector of the one or more column-index vectors, wherein each product is associated with a row of the partition, and
• s respective partial sums of the products associated with the s rows of the partition;
• and
• wherein for each group of s rows of the sparse matrix, a vector processor of the plurality of vector processors is configured to generate s final sums from the s respective partial sums.