Interface circuit, digital circuit, communication module, and communication device

Abstract

An interface circuit includes a first storage circuit that holds first timer selection information indicating which of a plurality of timers is to be selected; a second circuit including a first circuit that performs a counter operation, and a register update signal generation circuit that outputs, based on an output of the first circuit, a first register update signal for updating a register, the second circuit being capable of operating as any one of the plurality of timers; and a control circuit that controls, based on the first timer selection information from the first storage circuit and counter identification information that is received from an external device and that indicates any one of a plurality of counters associated with the plurality of timers, whether to enable or disable write to the first circuit or read from the first circuit.

Dependencies are inferred from the claim text.