Circuit device with multiple parallel data paths
AssigneeTexas Instruments Incorporated
InventorsBrian Jason KARGUTH, Charles Lance FUOCO, Samuel Paul VISALLI, Michael Anthony DENIO
Life of this patent
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Abstract
An integrated circuit (IC) includes first and second memory devices and a bridge. The IC also includes a first interconnect segment coupled between the first memory device and the bridge. The IC further includes a second interconnect segment coupled between the first and second memory devices, and a third interconnect segment coupled between the bridge and the second memory device. The IC includes a first DMA circuit coupled to the first interconnect segment, and a second DMA circuit coupled to the second interconnect segment. A fourth interconnect segment is coupled between the first and second DMA circuits.
Claims20
A system comprising:
- a processing unit;
- a first data path configured to couple a source device to a target device, wherein the first data path is a blocking data path and includes:
- a first interconnect segment configured to couple to the source device;
- a second interconnect segment configured to couple to the target device;
- and
- a bridge circuit coupled between the first interconnect segment and the second interconnect segment;
- a data read circuit coupled to the processing unit and configured to couple to the source device;
- a data write circuit coupled to the processing unit and configured to couple to the target device;
- and
- a second data path coupled between the data read circuit and the data write circuit, wherein the second data path is a non-blocking data path.
A system comprising:
- a source device;
- a target device;
- a first data path coupled between the source device and the target device, wherein the first data path is a blocking data path and includes:
- a first interconnect segment coupled to the source device;
- a second interconnect segment coupled to the target device;
- and
- a bridge circuit coupled between the first interconnect segment and the second interconnect segment;
- a read circuit coupled to the source device;
- a write circuit coupled to the target device;
- and
- a second data path coupled between the read circuit and the write circuit, wherein the second data path is a non-blocking data path.
A device comprising:
- a first data path configured to couple between a source device and a target device, wherein the first data path is a blocking data path and includes:
- a first interconnect segment coupled to the source device;
- a second interconnect segment coupled to the target device;
- and
- a bridge circuit coupled between the first interconnect segment and the second interconnect segment;
- a read circuit configured to couple to the source device;
- a write circuit configured to couple to the target device;
- and
- a second data path coupled between the read circuit and the write circuit, wherein the second data path is a non-blocking data path.
Dependencies are inferred from the claim text.