Packet Cache System and Method

A packet cache system comprising:

• a cache memory allocator for receiving a memory address corresponding to a non-cache memory and allocated to a packet, and associating the memory address with a cache memory address;
• a hash table for storing the memory address and the cache memory address, with the memory address as a key and the cache memory address as a value;
• a cache memory for storing the packet at a location indicated by the cache memory address;
• an eviction engine for determining one or more cached packets to remove from the cache memory and place in the non-cache memory when occupancy of the cache memory is high;
• and
• a reorder engine for receiving a read request comprising a read address corresponding to the non-cache memory and allocated to a desired packet to be read from either the cache memory or the non-cache memory, and for storing the desired packet, upon reading from either the cache memory or the non-cache memory, into a reorder buffer such that the desired packet is supplied in response to the read request at a timing proper relative to a timing of other read requests.

A method for storing packets in memory and reading the packets from memory, comprising:

• allocating a memory address, corresponding to a non-cache memory, to a packet;
• associating the memory address with a cache memory address;
• storing the memory address and the cache memory address in a hash table, with the memory address as a key and the cache memory address as a value;
• storing the packet in cache memory at a location indicated by the cache memory address;
• when occupancy of the cache memory is high, determining one or more cached packets to remove from the cache memory and place in the non-cache memory;
• receiving a read request comprising a read address corresponding to the non-cache memory and allocated to a desired packet to be read from either the cache memory or the non-cache memory;
• and
• storing the desired packet, upon reading from either the cache memory or the non-cache memory, into a reorder buffer such that the desired packet is supplied in response to the read request at a timing proper relative to a timing of other read requests.