Processor support for using cache way-locking to simultaneously record plural execution contexts into independent execution traces

A processor comprising:

• a processing unit;
• a memory cache;
• and
• control logic that configures the processor to record plural execution contexts into independent execution traces by:
• partitioning the memory cache into a plurality of memory cache subsets that include:
• (i) a first memory cache subset comprising a first set of memory cache ways that are locked to a first execution context whose execution at the processor is being recorded into a first trace buffer, and (ii) a second memory cache subset comprising a second set of memory cache ways that are locked to a second execution context whose execution at the processor is being recorded into a second trace buffer;
• detecting a first memory operation by the first execution context into the second memory cache subset;
• and
• in response to detecting the first memory operation, performing at least one of:
• (i) when the first memory operation causes a first influx into the second memory cache subset, initiating logging of the first influx to the second trace buffer;
• (ii) when the first memory operation is a first read from the second memory cache subset, initiating logging of the first read to the first trace buffer;
• or
• (iii) when the first memory operation is a first write to the second memory cache subset, performing one of (a) initiating logging of the first write to the second trace buffer, or (b) evicting a first cache line that is a target of the first write.

A method, implemented at a processor that includes a processing unit and a memory cache, the method comprising:

• partitioning the memory cache into a plurality of memory cache subsets that include:
• (i) a first memory cache subset comprising a first set of memory cache ways that are locked to a first execution context whose execution at the processor is being recorded into a first trace buffer, and (ii) a second memory cache subset comprising a second set of memory cache ways that are locked to a second execution context whose execution at the processor is being recorded into a second trace buffer;
• detecting a first memory operation by the first execution context into the second memory cache subset;
• and
• in response to detecting the first memory operation, performing at least one of:
• (i) when the first memory operation causes a first influx into the second memory cache subset, initiating logging of the first influx to the second trace buffer;
• (ii) when the first memory operation is a first read from the second memory cache subset, initiating logging of the first read to the first trace buffer;
• or
• (iii) when the first memory operation is a first write to the second memory cache subset, performing one of (a) initiating logging of the first write to the second trace buffer, or (b) evicting a first cache line that is a target of the first write.