Cache structure for high performance hardware based processor
AssigneeHyannis Port Research, Inc.
InventorAnthony D. Amicangioli
Life of this patent
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Abstract
A high performance computing system and methods, such as may be used to implement functions such as a matching book processor or data feed service. The system and methods organize data representing orders in a particularly efficient cache line structures referred to as tiles. The tiles each include order data for a given instrument, side, and price. The order data within each tile is further configured as an access node that includes minimal data needed to process the order. The array of access nodes is further organized into one or more prioritized collections of active and/or free access nodes.
Claims27
An electronic data processing system comprising:
- a data processor configured to perform one or more market functions;
- a memory, accessed by the data processor to configure data stored therein as one or more tiles, with each tile further comprising:
- an array of access nodes that represent open orders for a given instrument, side, and price;
- metadata fields that relate to the array of access nodes;
- and
- one or more head and/or tail references that organize the array of access nodes into one or more prioritized collections of active and/or free access nodes.
A computer program product in a computer-readable medium for use in a data processing system for executing a market function, the computer program product comprising:
- first instructions for receiving access nodes, each access node referencing a cell data structure representing order data associated with an instrument, side and price;
- second instructions for inserting the access nodes into one or more tiles, each of the one or more tiles comprising:
- an array of the access nodes for a given instrument, side, and price;
- metadata fields that relate to additional order data for the given instrument, side, and price;
- and
- at least a head and a tail reference organizing the access nodes in the array into one or more prioritized collections;
- and
- third instructions for processing the array of access nodes to execute the market function.
An electronic data processing system comprising:
- one or more data processors;
- and
- one or more memories, accessed by the one or more data processors to configure data stored therein as one or more tiles, the one or more memories comprising:
- an on-chip Block Random Access Memory (Block RAM) located on a semiconductor chip with the at least one of the one or more data processors;
- and
- an off-chip Dynamic Random Access Memory (DRAM);
- wherein each of the one or more tiles comprises:
- an array of access nodes that represent orders for a particular instrument, side and price (ISP);
- and
- one or more head and/or tail references that organize the access nodes into one or more prioritized collections of active access nodes and a collection of free access nodes;
- and
- wherein the one or more data processors are further configured for:
- receiving a request for an access node at a given ISP;
- loading a tile for the given ISP from the DRAM into the Block RAM;
- locating in the Block RAM the requested access node in the tile for the given ISP loaded in the Block RAM;
- and
- returning from the Block RAM the requested access node from the tile for the given ISP loaded in the Block RAM.
Dependencies are inferred from the claim text.