Pipeline architecture for bitwise multiplier-accumulator (mac)

A unit for accumulating a plurality N of multiplied M bit values, the unit comprising:

• a first row of input units to receive a pipeline of the bits of a multiplicand A, where each input unit receives one bit of multiplicand A;
• a second row of input units to the left of first row of input units, the second row of input units to receive a pipeline of the bits of a multiplicand B, where each input unit receives one bit of multiplicand B;
• a bit-wise multiplier located below said first row of input units and comprising multiplier bit-line processors formed into rows and columns, a first M rows of said bit-wise multiplier to bit-wise multiply bits of a current multiplicand A with one bit of a current multiplicand B and a second M rows of said bit-wise multiplier to handle sum and carry values between said bits;
• and
• a bit-wise accumulator to the right of bit-wise multiplier comprising a column of accumulator bit-line processors, each accumulator bit-line processor to accumulate output of a row of said bit-wise multiplier thereby to accumulate said multiplicands during the pipelining process.