Processor instruction exception handling
AssigneeAkeana, Inc.
InventorsRicardo Ramirez, Rabin Sugumar
Life of this patent
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AssigneeAkeana, Inc.
InventorsRicardo Ramirez, Rabin Sugumar
Estimating the term…
Techniques for instruction execution based on processor instruction exception handling are disclosed. A processor core is accessed. The processor core executes at least one instruction thread. The processor core executes one or more instructions out of order. An ordered list of instructions is maintained. The ordered list is based on instructions that are presented to the processor core for execution. The ordered list is organized using one or more pointers. An execution exception is detected in the processor core. The execution exception corresponds to one of the instructions in the ordered list. The execution exception requires initiating an exception handling routine. An effective age of an instruction in the ordered list is determined. The effective age corresponds to the execution exception. The exception handling routine is initiated, based on matching the effective age of an instruction in the ordered list with one of the one or more pointers.
A processor-implemented method for instruction execution comprising:
A computer program product embodied in a non-transitory computer readable medium for instruction execution, the computer program product comprising code which causes one or more processors to perform operations of:
A computer system for instruction execution comprising:
Dependencies are inferred from the claim text.