Register renaming

A data processing method comprising:

• predicting, for a given instruction, a sector identifier identifying a sector of a physical register array to be used for a destination register of the given instruction, the physical register array comprising a plurality of sectors having one or more different access properties, each sector of the plurality of sectors comprising at least one physical register, wherein predicting the sector identifier for the given instructions comprises selecting the sector identifier in dependence on prediction information learnt from performance monitoring information indicative of performance achieved for a sequence of instructions when using different sector identifiers for the given instruction;
• mapping a destination architectural register identifier specified by the given instruction to a destination physical register in the sector identified by the sector identifier predicted for the given instruction;
• and
• executing the given instruction and generating a result to be written to the destination physical register mapped to the destination architectural register identifier.

A data processing apparatus comprising:

• a physical register array comprising a plurality of sectors having one or more different access properties, each sector of the plurality of sectors comprising at least one physical register;
• prediction circuitry to predict, for a given instruction, a sector identifier identifying one of the sectors of the physical register array to be used for a destination register of the given instruction and a delay indicator for controlling scheduling of one or more subsequent instructions after the given instruction, wherein the prediction circuitry is configured to predict the sector identifier and the delay indicator in dependence on prediction information learnt from performance monitoring information indicative of performance achieved for a sequence of instructions when using different sector identifiers and different delay indicators for the given instruction;
• register rename circuitry to map a destination architectural register identifier specified by the given instruction to a destination physical register in the sector identified by the sector identifier predicted by the prediction circuitry;
• execution circuitry to execute the given instruction and generate a result to be written to the destination physical register mapped to the destination architectural register identifier by the register rename circuitry;
• and
• scheduling circuitry to schedule timing of execution of one or more of the subsequent instructions based on the delay indicator predicted by the prediction circuitry.