Branch target buffer operation with auxiliary indirect cache

A computer program product embodied in a non-transitory computer readable medium for branch prediction, the computer program product comprising code which causes one or more processors to generate semiconductor logic for:

• accessing a processor core, wherein the processor core is coupled to memory, and wherein the processor core includes branch prediction circuitry, wherein the branch prediction circuitry includes a branch target buffer (BTB) and an indirect branch target buffer (BTBI);
• reading a hashed program counter within the processor core;
• searching the BTB and the BTBI, wherein the searching the BTB is accomplished with the hashed program counter and the searching the BTBI is accomplished with the hashed program counter and branch history information;
• matching a predicted branch target address within the BTBI or the BTB, wherein the matching within the BTBI is based on an indirect branch instruction, and wherein the matching within the BTB is based on other branch instruction types;
• deciding that the predicted branch target address that was matched is predicted taken;
• and
• directing the processor core to fetch a next instruction from the predicted branch target address.

An apparatus for branch prediction comprising:

• a processor core coupled to memory, wherein the processor core and the memory are used to perform operations comprising:
• accessing the processor core, wherein the processor core is coupled to the memory, and wherein the processor core includes branch prediction circuitry, wherein the branch prediction circuitry includes a branch target buffer (BTB) and an indirect branch target buffer (BTBI);
• reading a hashed program counter within the processor core;
• searching the BTB and the BTBI, wherein the searching the BTB is accomplished with the hashed program counter and the searching the BTBI is accomplished with the hashed program counter and branch history information;
• matching a predicted branch target address within the BTBI or the BTB, wherein the matching within the BTBI is based on an indirect branch instruction, and wherein the matching within the BTB is based on other branch instruction types;
• deciding that the predicted branch target address that was matched is predicted taken;
• and
• directing the processor core to fetch a next instruction from the predicted branch target address.