Branch target buffer access systems and methods
AssigneeMicrosoft Technology Licensing, LLC
InventorsSomasundaram ARUNACHALAM, Daren Eugene STREETT, Richard William DOING
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Abstract
Embodiments of the present disclosure include techniques for branch prediction. A branch predictor may be included in a processor. The branch predictor may use heuristics to control lookups against multiple different memory caches in a branch target buffer. In one embodiment, a branch predictor monitors successful lookups and a lookup is performed against one cache before another cache based on a number of successful lookups. In another embodiment, lookups are performed against different caches based on a current available capacity of a fetch target queue.
Claims20
A processor comprising:
- a branch predictor comprising:
- a branch target buffer comprising a plurality of memory caches, the plurality of memory caches storing different numbers of entries, the entries comprising branch target addresses;
- and
- a branch logic circuit configured to generate a plurality of instruction addresses and to lookup, in the branch target buffer, branch target addresses that match the instruction addresses;
- and
- a fetch target queue storing a plurality of instruction addresses from the branch predictor,
- wherein the branch logic circuit monitors successful lookup matches to the plurality of memory caches, and
- wherein the branch logic circuit performs a lookup in a first memory cache of the plurality of memory caches before a second memory cache of the plurality of memory caches based on one of:
- the first memory cache having a higher number of successful lookup matches than the second memory cache, or
- a current available storage capacity of the fetch target queue.
A method of predicting branches in a processor comprising:
- storing entries in a plurality of memory caches of a branch target buffer in a branch predictor, the plurality of memory caches storing different numbers of entries, the entries comprising branch target addresses;
- generating a plurality of instruction addresses in the branch predictor;
- performing, by a branch logic circuit in the branch predictor, a lookup in the branch target buffer of branch target addresses that match the instruction addresses;
- storing, in a fetch target queue, a plurality of instruction addresses from the branch predictor;
- and
- monitoring, by the branch logic circuit, successful lookup matches to the plurality of memory caches,
- wherein the branch logic circuit performs a lookup in a first memory cache of the plurality of memory caches before a second memory cache of the plurality of memory caches based on one of:
- the first memory cache having a higher number of successful lookup matches than the second memory cache, or
- a current available storage capacity of the fetch target queue.
Dependencies are inferred from the claim text.