Systems, methods, and apparatuses for matrix operations

A non-transitory machine readable medium having stored thereon at least an instance of a single matrix instruction which when processed by a machine causes the machine to perform a method comprising:

• decoding the single matrix instruction having fields for an opcode, a plurality of identifiers corresponding to a first plurality of 4-bit integer data elements of a first source matrix, a second plurality of 4-bit integer data elements of a second source matrix, a plurality of doubleword integer source data elements of a third source matrix, and a plurality of doubleword integer result data elements of a result matrix, and bits indicating whether one or both of the first and second plurality of 4-bit integer data elements are signed or unsigned;
• and
• executing the single matrix instruction by
• performing a parallel multiplication of each 4-bit integer data element of a first subset of the first plurality of 4-bit integer data elements with a corresponding 4-bit integer data element of a first subset of the second plurality of 4-bit integer data elements to generate a plurality of products;
• and
• adding the plurality of products to a corresponding doubleword integer source data element of the plurality of doubleword integer source data elements to generate a corresponding doubleword integer result data element of the plurality of doubleword integer result data elements.

A system comprising:

• a processor core comprising decode circuitry to decode a single matrix instruction having fields for an opcode, a plurality of identifiers corresponding to a first plurality of 4-bit integer data elements of a first source matrix, a second plurality of 4-bit integer data elements of a second source matrix, a plurality of doubleword integer source data elements of a third source matrix, and a plurality of doubleword integer result data elements of a result matrix, and bits indicating whether one or both of the first and second plurality of 4-bit integer data elements are signed or unsigned;
• and
• an accelerator coupled to the processor core, the accelerator comprising:
• execution circuitry to execute the decoded single matrix instruction, the execution circuitry including a multiply-accumulate circuit, comprising:
• a set of multipliers to perform a parallel multiplication of each 4-bit integer data element of a first subset of the first plurality of 4-bit integer data elements with a corresponding 4-bit integer data element of a first subset of the second plurality of 4-bit integer data elements to generate a plurality of products;
• and
• an accumulator to add the plurality of products to a corresponding doubleword integer source data element of the plurality of doubleword integer source data elements to generate a corresponding doubleword integer result data element of the plurality of doubleword integer result data elements.